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? semiconductor MSM7650 1/34 ? semiconductor MSM7650 ntsc/pal digital encoder general description the MSM7650 is a digital ntsc/pal encoder. by inputting digital image data conforming to ccir rep624-4, it outputs analog composite video signals and analog s video signals. for the scanning system, interlaced or noninterlaced mode can be selected. since the MSM7650 is provided with pins dedicated to overlay function, text and graphics can be superimposed on a video signal. in addition, this encoder has an internal 9-bit dac. so, when compared with using a conventional analog encoder, the number of components, the board space, and points of adjustment can greatly be reduced, thereby realizing a low cost and high-accuracy system. the host interface provided conforms to philips's i 2 c specifications, which reduces interconnections between this encoder and mounting components. the internal synchronization signal generator (ssg) allows the MSM7650 to operate in master or slave mode. features ? video signal system: ntsc/pal ? scanning system: interlaced/noninterlaced ? input digital level: conforms to itu-601 (ccir601) ? input-output timing: conforms to ccir rep 624-4 ? input signal (sampling ratio) y:cb:cr (4:2:2/4:1:1) ? supported sampling rates ? ntsc 4fsc (14.32 mhz) ? ntsc itu-r601 (13.5 mhz) ? ntsc square pixel (12.27 mhz) ? pal itu-r601 (13.5 mhz) ? pal square pixel (14.75 mhz) ? internal ssg circuit (internally generates sync signals) ? operation by external synchronization possible ? internal 3ch 9-bit dac (samples by double frequency) ? 3-bit title graphics can be displayed ?i 2 c-bus host interface function ? package 80-pin plastic qfp (qfp80-p-1420-0.80-bk) (product name: MSM7650gs-bk) e2f0003-27-x1 this version: jan. 1998 previous version: oct. 1997
? semiconductor MSM7650 2/34 applications ? video game equipment ? cd-rom ? electronic still camera ? video graphics board ? video printer ? videophone ? video camera ? video conference system ? scanner ? multimedia equipment ? image file system ? digital vtr
? semiconductor MSM7650 3/34 block diagram y limitter y level converter overlay control black & blank pedestal ipf c limitter & uv selector yd[7:0] cd[7:0] olr olg olb olc vsync_l hsync_l blank_l clkx1 u level converter interpolator + lpf v level converter interpolator + lpf yuv color generator dac dac ipf dac color burst generator subcarrier generator sync generator & timing controller i 2 c control logic test control logic ya cvbso ca ct [8:0] clkx2o reset_l test[4:1] tout[2:1] sda scl mode[2:0] interlace ms clkx2 x
? semiconductor MSM7650 4/34 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 65 79 78 77 76 75 74 73 72 71 70 69 68 67 66 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 40 26 27 28 29 30 31 32 33 34 35 36 37 38 39 v dd5 v dd3 gnd vsync_l hsync_l blank_l clkx1 clkx2 clkx2o x x_l v dd3 gnd ct8 ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 v dd5 gnd v dd3 nc vref fs comp agnd ya agnd av dd av dd cvbso agnd ca av dd gnd nc cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 v dd5 v dd3 gnd olr olg olb olc mode[0] mode[1] mode[2] interlace ms reset_l scl sda adrs tout2 tout1 test4 test3 test2 test1 gnd v dd3 nc : no-connection pin MSM7650 80-pin plastic qfp
? semiconductor MSM7650 5/34 pin descriptions (1/2) pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 to 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 i/o i/o i/o i i i o i o i i/o i i i o o o i i symbol v dd5 v dd3 gnd vsync_l hsync_l blank_l clkx1 clkx2 clkx2o x x_l v dd3 gnd ct8 to ct0 v dd5 gnd v dd3 nc vref fs comp agnd ya agnd av dd av dd cvbso agnd ca av dd gnd nc v dd3 gnd test1 test2 test3 description 5.0v power supply 3.3v power supply digital gnd vertical sync signal polarity is negative. output pin in master mode; input pin in slave mode. horizontal sync signal polarity is negative. output pin in master mode; input pin in slave mode. composite blank signal. polarity is negative. pixel clock input pin double pixel clock input pin double pixel clock output pin test pin. normally, fixed to "0". test pin 3.3v power supply digital gnd input pin for testing. normally, fixed to "0" or "1". 5.0v power supply digital gnd 3.3v power supply not connected reference voltage for dac dac full scale adjustment pin dac phase compensation pin analog gnd analog luminance signal output pin analog gnd analog power supply analog power supply analog composite video signal output pin analog gnd analog chrominance signal output pin analog power supply digital gnd not connected 3.3v power supply digital gnd input pin 1 for testing. normally, fixed to "0". input pin 2 for testing. normally, fixed to "0". input pin 3 for testing. normally, fixed to "0".
? semiconductor MSM7650 6/34 pin descriptions (2/2) pin 46 47 48 49 50 51 52 53 54 55 to 57 58 59 60 61 62 63 64 65 to 72 73 to 80 i/o i o o i i/o i i i i i i i i i i i symbol test4 tout1 tout2 adrs sda scl reset_l ms interlace mode[2] to mode[0] olc olb olg olr gnd v dd3 v dd5 yd0 to yd7 cd0 to cd7 description input pin 4 for testing. normally, fixed to "0". output pin for testing output pin for testing i 2 c-bus subaddress setting pin. one of two addresses switchable can be selected as subaddress. 1: 1000110/0: 1000100 i 2 c-bus data pin i 2 c-bus clock pin system reset pin. "1" at an open state by an internal pull-up resistor operation mode select signal pin for synchronization circuit. 1: master/0: slave. "1" at an open state by an internal pull-up resistor interlace/noninterlace select signal pin. 1: interlaced/0: noninterlaced. "1" at an open state by an internal pull-up resistor video mode select pins these pins are valid when mr[7] is "1". transparent control signal overlay signal is displayed when this pin is "h". overlay text color (blue component) overlay text color (green component) overlay text color (red component) digital gnd 3.3v power supply 5.0v power supply digital image luminance signal data input pin level is based on itu-601. yd7 is msb. digital image chrominance signal data input pin level is based on itu-601. cd7 is msb. 000: ntsc ccir 100: pal ccir "000" at an open state by an internal pull-down resistor 001: ntsc square pixel 101: pal square pixel 010: ntsc 4fsc
? semiconductor MSM7650 7/34 absolute maximum ratings parameter power supply voltage input voltage analog output current power consumption storage temperature symbol v dd5 v dd3 av dd v i i o p w t stg condition ta=25c ta=25c ta=25c ta=25c rating C0.3 to +7 C0.3 to +4.5 C0.3 to +4.5 C0.3 to v dd5 +0.3 40 800 C55 to +150 unit v v ma mw c recommended operating conditions parameter power supply voltage power supply voltage low level input voltage symbol v dd5 v dd3 av dd gnd agnd v ih1 v il condition ta=25?c ta=25?c ta=25?c ta=25?c ta=25?c sda, clkx1, except clkx2, ta=25?c typ. 5.0 3.3 3.3 0.0 0.0 unit v v v v operating temperature range ta ?c min. 4.5 3.0 3.0 2.2 0.0 0.0 max. 5.5 3.6 3.6 v dd5 0.5 70 external reference voltage (*1) vrefex 1.25 v da current setting resistance (*2) riadj 330 w da output load resistance r l 75 w high level input voltage v ih2 sda, ta=25?c v 0.8 v dd5 v dd5 v ih3 clkx1,clkx2, ta=25?c v 2.4 v dd5 (*1) when external reference voltage is not supplied, internal reference voltage is as follows. internal reference voltage vrefin v 1.15 1.45 (*2) a volume control resistor of approx. 500 w is recommendable for adjusting the output current.
? semiconductor MSM7650 8/34 electrical characteristics dc characteristics parameter symbol v oh condition i oh =C4ma (*1) i oh =C8ma (*2) i ol =4ma (*1) typ. unit low level output voltage v ol i ol =8ma (*2) v min. 0.8v dd5 0 max. v dd5 0.6 high level output voltage v input leak current i i v i =gnd to v dd5 m a C10 10 output leak current i o v i =gnd to v dd5 (*3) m a C10 10 power supply current (operating) i ddo clkx1=13.5mhz 120 ma 140 power supply current (standby) i dds reset_l="l" 65 ma 80 i 2 c-bus sda output voltage sdav l low level, i ol =3ma v 0 0.4 i 2 c-bus sda output current sdai o during acknowledge ma 3 (ta=0 to +70c, v dd3 =3.3v0.3v, v dd5 =5v10%) internal reference voltage vrefin v 1.15 1.45 da output load resistance r l 75 w integral linearity sinl 2 lsb differential linearity sdnl 1 lsb clkx2=27.0mhz clkx1=clkx2=0hz (*1) hsync_l, vsync_l, sda, to, ct[7:0] (*2) clkx2o (*3) sda
? semiconductor MSM7650 9/34 ac characteristics parameter symbol condition min. typ. max. unit (ta=0 to +70c, v dd3 =3.3v0.3v, v dd5 =5v0.5v) clkx cycle time t s pal square pixel 67.8 ns ntsc 4fsc 69.8 ns ntsc square pixel 81.5 ns itu-rs601 74.1 ns input data setup time input data hold time output delay time clkx2o delay time t s1 t h1 t d1 t d2 7.03 ns 9.48 ns 18.35 24.12 ns 7.69 9.53 ns clock cycle time t c_scl ns rpull_up=4.7k w clock duty cycle t d_scl 50 % low level cycle t l_scl ns rpull_up=4.7k w 200 100
? semiconductor MSM7650 10/34 clkx1 reset_l, hsync_l, vsync_l, yd[7:0], cd[7:0], ms, mode[2:0], interlace, olr, olg, olb, olc hsync_l, vsync_l clkx2 clkx2o valid t d1 t h1 t s1 invalid t d2 input timing output timing valid scl sda t c_scl t l_scl clkx2 tccd1 clkx1 clkx2 tccd2 clkx1 the phase relations between clkx1 and clkx2 are shown below. 1. when the clkx1 pulse rises later than the clkx2 pulse. 2. when the clkx1 pulse rises earlier than the clkx2 pulse. tccd1: 20.14 [ns] tccd2: 3.27 [ns]
? semiconductor MSM7650 11/34 block functional description y limitter this block limits the contents outside the specified range as follows for input luminance signal yd specified by the itu-601 standard. ? signals are limited to yd = 235 when yd_in > 235 ? signals are limited to yd = 16 when yd_in < 16 ? in other cases, signals are fed as is to next processing c limitter this block limits the contents outside the specified range as follows for input chrominance signals specified by the itu-601 standard. the input chrominance signal is output as a 2s complement format. the processing procedure follows. 1) format processing for input chrominance signals ? if mr [6] = 0, cd is in offset binary format. cd is converted to 2s complement format and is fed to next processing. ? if mr [6] = 1, cd is in 2s complement format. cd is fed as is to next processing. 2) clipping processing ? signals are limited to cd = 112 when cd>112 ? signals are limited to cd = -112 when cd < -112 ? in other cases, signals are fed to next processing in addition, this block separates u and v components from the input chrominance signal cd into which data of u and v components has been inserted using time sharing, and then passes signals to the next process. ? y level converter converts itu-601 standard luminance signal level to dac digital input level. ? u level converter converts itu-601 standard chrominance signal level to dac digital input level. ? v level converter converts itu-601 standard chrominance signal level to dac digital input level. ? yuv color generator this block generates luminance and chrominance signals from over lay color signals olr, olg and olb. control signals (cr [2:0] ) control the output content (overlay or color bar) and output level (100%, 75%, 50%, 25%). ? overlay control this block selects input image data or yuv color generator output signals. it is determined by the level of the control signal (olc, cr [2]), as shown below: cr [2] = 1, olc = ?: selects color bar signal (yuv color generator output signal). cr [2] = 0, olc = 1: selects overlay signal (yuv color generator output signal). cr [2] = 0, olc = 0: selects input image data.
? semiconductor MSM7650 12/34 ? black & blank pedestal this block adds sync signals at the luminance side to luminance signals. ? interpolator +lpf this block executes data interpolation and the elimination of high frequency components by lpf for input chrominance signals. both 4:2:2 and 4:1:1 signals are processed. ?i 2 c control logic this is the serial interface block based on i 2 c standard of phillips corporation. internal registers mr and cr can be set from the master side. when writing to the internal registers other than mr [5] (black level control) and cr [1:0] (overlay level), written contents are immediately set to them. it is during the vertical blanking period that written contents are set to mr [5] and cr [1:0]. ? sync generator & timing controller this block generates sync signals and control signals. this block is operated in slave mode, which performs external synchronization, and in master mode, which internally generates sync signals. ? color burst generator outputs u and v components of amplitude of burst signals. ? subcarrier generator executes color subcarrier generation. ? interpolation filter (ipf) this block performs upsampling at clk x 2 (double speed clkx1) for luminance signals and chrominance signals modulated with clkx1. interpolation processing is executed in this process.
? semiconductor MSM7650 13/34 input data format input digital level the content conforms to ccir601 (itu-601). for chrominance input cb and cr, 2s complement and offset binary formats are available by setting of internal registers. input values outside the specified range are limited by internal clipping processing. the valid input levels of luminance signal and chrominance signal are shown below. 235 16 y data digital level 100% white level black level 240(112) 16(C112) c data digital level 128(0) note) values are in offset binary format. (values in parenthesis are in 2's complement format.) input luminance signal level input chrominance signal level basic pixel sampling ratio 4:2:2 and 4:1:1 sampling are supported. an internal register can control the sampling ratio. yd y1 y2 y3 y4 y5 y6 clkx1 cd u1 v1 u3 v3 u5 v5 yd y1 y2 y3 y4 y5 y6 clkx1 cd u1 v1 u5 v5 4:2:2 sampling 4:1:1 sampling
? semiconductor MSM7650 14/34 output format output level when the output level of the operation mode is ntsc, the content of the output level differs depending on setup level setting by internal registers. when the setup level is set, data is output with black-white as 92.5 ire. when the setup level is not set, data is output with black-white as 100 ire. however, the setup level setting above is valid only when ntsc is selected as operation mode, and setup level does not exist when pal is selected as the operation mode. when the contents of 100% luminance order color bar are input to the encoder, the dac input level is as follows. C20 0 7.5 11 20 30 41 59 70 89 100 133 C40 59 114 135 144 169 197 227 276 307 359 389 480 4 dac data lumi [ire] composite wave form (ntsc) white yellow cyan green magenta red blue black ntsc composite signal (setup: 7.5 ire)
? semiconductor MSM7650 15/34 0 11 30 41 59 70 89 100 C40 114 144 197 227 276 307 359 389 4 dac data lumi [ire] y wave form (ntsc) white yellow cyan green magenta red blue black ntsc y signal output (setup: 0) C20 0 C59 C63 20 44 59 63 C44 201 256 94 83 311 377 418 429 135 dac data lumi [ire] c wave form (ntsc) yellow cyan green magenta red blue color burst ntsc c signal output (setup: 0)
? semiconductor MSM7650 16/34 C21.5 0 11 21.5 30 41 59 70 89 100 133 C43 63 122 153 181 205 235 285 315 367 397 488 4 dac data lumi [ire] composite wave form (pal) white yellow cyan green magenta red blue black pal composite signal
? semiconductor MSM7650 17/34 0 11 30 41 59 70 89 100 C43 122 153 205 235 285 315 367 397 4 dac data lumi [ire] y wave form (pal) white yellow cyan green magenta red blue black pal y signal output C21.5 0 C59 C63 21.5 44 59 63 C44 197 256 94 83 315 377 418 429 135 dac data lumi [ire] c wave form (pal) yellow cyan green magenta red blue color burst pal c signal output
? semiconductor MSM7650 18/34 clock timing input data timing input data and sync signals are fed into the encoder at the rising edge of the clock. input data is handled as valid pixel data when t start passes after the falling edge of hsync_l. chrominance signal of input data at this time is regarded as cb. don't care don't care yd, cd olc, olr olg, olb hsync_l clkx1 blank_l t start t act t s1 t h1 valid data active video line video data input timing input data is recognized as valid pixel data when input signal blank_l is high in the t act period. when blank_l is high during the blanking period, however, input data is not output as valid pixel data since processing to maintain blanking period is internally in-progress. the values of t start differ slightly in master mode and slave mode. the values of t start are as follows. operation mode ccir 601 ntsc square pixel ntsc 4fsc ntsc ccir pal square pixel pal in master mode t sta (ts) 126 141 115 134 154 operation mode ccir 601 ntsc square pixel ntsc 4fsc ntsc ccir pal square pixel pal in slave mode t sta (ts) 129 144 118 137 157 t sta Ct s1 =t start
? semiconductor MSM7650 19/34 internal synchronization output timing input and output timing of hsync_l and vsync_l in master mode is as follows. t d1 t d1 clkx1 hsync_l vsync_l output timing of internal synchronization clk1, hsync_l and vsync_l ya vsync_l 5235245251234567 17 18 output timing of internal synchronization vsync_l
? semiconductor MSM7650 20/34 output timing output timing conforms to ccir rep 624-4. when the operation method is ntsc/pal and the scanning method is interlace/noninterlace, the output wave form content of composite signals are as follows. 25926026126226312345678 171819 field 1 reference sub-carrier phase negative half cycle burst relative 180 to b-y axis positive half cycle burst relative 180 to b-y axis a b c d e 25926026126226312345678 171819 field 2 reference sub-carrier phase a b c d e 25926026126226312345678 171819 field 3 reference sub-carrier phase a b c d e 25926026126226312345678 171819 field 4 reference sub-carrier phase a b c d e output timing (interlaced ntsc)
? semiconductor MSM7650 21/34 period odd field (even field) 259.5 to 262.5h 1 to 3h 4 to 6h 1 to 6,259.5 to 262.5h 1 to 17,259.5 to 262.5h name first equalizing pulse period (3h) vertical synchronization period (3h) second equalizing pulse period (3h) burst pause period vertical blanking period (20h) symbol a b c d e output timing (interlaced ntsc)
? semiconductor MSM7650 22/34 26026126212345678 171819 continuous odd field reference sub-carrier phase negative half cycle burst relative 180 to b-y axis positive half cycle burst relative 180 to b-y axis a b c d e 26026126212345678 171819 reference sub-carrier phase a b c d e 26026126212345678 171819 continuous even field reference sub-carrier phase a b c d e 26026126212345678 171819 reference sub-carrier phase a b c d e output timing (noninterlaced ntsc) period continuous odd field 261 to 262h 1 to 3h 4 to 6h 261 to 6h 261 to 17h name first equalizing pulse period (2h) vertical synchronization period (3h) second equalizing pulse period (2h) burst pause period vertical blanking period (19h) symbol a b c d e continuous even field 261.5 to 262h 1 to 3h 4 to 6h 261.5 to 6h 261.5 to 17.5h output timing (noninterlaced ntsc)
? semiconductor MSM7650 23/34 output timing (interlaced pal) output timing (interlaced pal) period filed 1,5 311 to 312.5h 1 to 2.5h 2.5 to 5h 1 to 6,310 to 312.5h 1 to 22.5,311 to 312.5h name first equalizing pulse period (2.5h) vertical synchronization period (2.5h) second equalizing pulse period (2.5h) burst pause period vertical blanking period (25h) symbol a b c d e filed 3,7 311 to 312.5h 1 to 2.5h 2.5 to 5h 1 to 5,311 to 312.5h 1 to 22.5,311 to 312.5h filed 2,6 311 to 312.5h 1 to 2.5h 2.5 to 5h 1 to 5.5,308.5 to 312.5h 1 to 22.5,311 to 312.5h filed 4,8 311 to 312.5h 1 to 2.5h 2.5 to 5h 1 to 6.5,309.5 to 312.5h 1 to 22.5,311 to 312.5h 30931031131231312 345678 232425 field 1,5 burst phase +135 +v burst phase -135 -v a b c d e field 2,6 30931031131231312 345678 232425 a b c d e 30931031131231312 345678 232425 field 3,7 a b c d e field 4,8 30931031131231312 345678 232425 a b c d e
? semiconductor MSM7650 24/34 31031131212345678 232425 continuous odd field burst phase +135 +v burst phase -135 -v a b c d e 309 31031131212345678 232425 a b c d e 309 31031131212345678 232425 continuous even field a b c d e 309 31031131212345678 232425 a b c d e 309 output timing (noninterlaced pal) output timing (noninterlaced pal) period continuous odd field 311 to 312h 1 to 2.5h 2.5 to 5h 311 to 6h 311 to 22h name first equalizing pulse period (2h) vertical synchronization period (2.5h) second equalizing pulse period (2.5h) burst pause period vertical blanking period (24h) symbol a b c d e continuous even field 311.5 to 312h 1 to 2.5h 2.5 to 5h 311.5 to 6h 311.5 to 22.5h
? semiconductor MSM7650 25/34 equalizing pulse vertical synchronization period setting content of equalizing pulse vertical synchronization period (ts is sampling clock cycle in each mode) ntsc ccir601 pal ccir601 ntsc square pixel ntsc 4fsc pal square pixel q 31ts 32ts 28ts 33ts 35ts w 398ts 369ts 332ts 387ts 403ts e 64ts 63ts 58ts 68ts 69ts 1/2h 429ts 432ts 390ts 455ts 472ts q w e 1/2h 1/2h q equalizing pulse width w vertical sync pulse width e serration q blanking level w (synchronizing+{blanking level) (2/3) e (synchronizing+{blanking level) (1/3) r synchronzing level r e w q equalizing pulse vertical equalizing pulse vertical synchronization period synchronization period setting content of horizontal blanking period horizontal blanking period q w e r t 1h q horizontal sync pulse width w burst signal output period e burst signal start r horizontal blanking period (excluding front porch) t front porch start q synchronzing level w (synchronizing+{blanking level) (1/3) e (synchronizing+{blanking level) (2/3) r blanking level t peak to peak value of burst r e w q t setting content of horizontal blanking period (ts is sampling clock cycle in each mode) ntsc ccir601 pal ccir601 ntsc square pixel ntsc 4fsc pal square pixel q 63ts 63ts 58ts 67ts 69ts w 31ts 31ts 31ts 36ts 34ts e 71ts 75ts 65ts 75ts 82ts r 127ts 142ts 116ts 135ts 155ts t 838ts 844ts 762ts 889ts 922ts total dots/1h 858 864 780 910 944
? semiconductor MSM7650 26/34 internally generated color bar output timing this function outputs a 100% and 75% luminance order color bar by setting internal registers. output timing of each color of the color bar is as follows. white yellow cyan green magenta red blue black q w e r t y u each color of color bar output timing ntsc ccir601 ntsc square pixel ntsc 4fsc pal ccir601 pal square pixel 1h 858ts 780ts 910ts 864ts 944ts u 750ts 682ts 795ts 757ts 827ts y 661ts 602ts 701ts 670ts 731ts t 572ts 521ts 607ts 582ts 635ts r 483ts 440ts 513ts 494ts 539ts e 394ts 359ts 419ts 406ts 443ts w 305ts 278ts 325ts 318ts 347ts q 216ts 197ts 230ts 230ts 251ts hblank 127ts 116ts 135ts 142ts 155ts operation mode (ts is sampling clock cycle) each color of color bar output timing
? semiconductor MSM7650 27/34 i 2 c-bus interface input/output timing basic input/output timing of i 2 c-bus interface is shown below. 12 789 ack 12 3-8 9 ack s start condition p stop condition data line stable: data valid change of data allowed scl sda msb t c.scl t l.scl i 2 c-bus basic input/output timing
? semiconductor MSM7650 28/34 i 2 c bus format basic input format of i 2 c-bus interface is shown below. s slave address a subaddress data n description start condition slave address 1000100 or 1000000, 8th bit is write signal. acknowledge. generated by slave subaddress byte data byte and acknowledge continues until data byte stop condition is met. symbol p stop condition slave address s subaddress0 a data 0 a a p slave address s subaddress1 a data 1 a a p ..... 1 cycle it is required to input the above-mentioned format from the start condition to the stop condition each time of writing a subaddress. for example, when writing the subaddresses 0 to 2, the format should be input three times. in case data of more than one byte are transferred, slave address s subaddress0 a data 0 a a p data n a p the 4th byte data and following data each are written over the same subaddress. if one of the following matters occurs, the encoder will not return "a" (acknowledge). ? the slave address does not match. ? a non-existent subaddress is specified. ? the read/write attribute of a register does not match "x" (read/write control bit). the input timing is shown below. s start condition p slave address scl sda 2 18 ack sub address 2 18 ack data 2 18 ack stop condition
? semiconductor MSM7650 29/34 contents of internal register setting all registers can be written by accessing 8 bits. "0" is read from an undefined bit. the contents of internal registers are shown below. (a value with "*" is the default.) mode register (mr) (default value after system reset: 10h) mr[7] override selects setting of external terminal or internal register *0: setting of external terminal is valid 1: setting of internal registers is valid mr[6] chroma format chrominance signal input format *0: offset binary 1: 2's complement mr[5] black level control black level setting (setup) note) valid only for ntsc. *0: black level 7.5 ire 1: black level 0 ire mr[4] synchronization mode selects master/slave operation of sync signal generator. 0: slave mode *1: master mode mr[3] pixel sampling ratio sampling ratio *0: 4:2:2 1: 4:1:1 mr[2:0] video mode select selects operation mode *000: ccir 601 ntsc 13.5 mhz 001: ntsc square pixel 12.27 mhz 010: ntsc 4fsc 14.32 mhz 100: ccir 601 pal 13.5 mhz 101: pal square pixel 14.75 mhz
? semiconductor MSM7650 30/34 command register (cr) (default value after system reset: 1bh) cr[7:5] undefined undefined cr[4] genlock selects sch phase management status 0: genlock off (subcarrier is self generated) *1: genlock on (management of sch phase is executed) cr[3] non-interlace scanning method in master mode 0: non-interlace *1: interlace cr[2] color bar output control of luminance order color bar for adjustment *0: input image data or overlay data 1: luminance order color bar cr[1:0] overlay level luminance signal output level control of overlay signals and luminance order color bar for adjustment 00: 25% 01: 50% 10: 75% *11: 100% d7 mr7 cr7 d6 mr6 cr6 d5 mr5 cr5 d4 mr4 cr4 data byte d3 mr3 cr3 d2 mr2 cr2 d1 mr1 cr1 d0 mr0 cr0 subaddress register function mode register (mr) command register (cr) 0 1
? semiconductor MSM7650 31/34 filter characteristics the characteristics of lpf used for color signal processing and interpolation filters used for upsampling processing are shown below. lpf for 411 color signals the following characteristics are when the clock frequency is 13.5 mhz. C100 C80 C60 C40 C20 0 01234567 411 interpolation+lpf frequency characteristic frequency [mhz] level [db] lpf for 422 color signals the following characteristics are when the clock frequency is 13.5 mhz. C100 C80 C60 C40 C20 0 01234567 422 interpolation + lpf frequency characteristic frequency [mhz] level [db]
? semiconductor MSM7650 32/34 up sampling filter the following characteristics are when the clock frequency is 27 mhz. C100 C80 C60 C40 C20 0 02468101214 up sampling filter frequency characteristic frequency [mhz] level [db]
? semiconductor MSM7650 33/34 application circuit example mode[2:0] ms interlace dip sw olr olg olb olc overlay controller blank_l hsync_l vsync_l clkx1 cd[7:0] cd[7:0] yd[7:0] yd[7:0] MSM7650 v ref fs comp ya lpf amp r1 cvbso lpf amp r2 ca lpf amp r2 c c typ. 1.25v r c scl sda i 2 c controller r i r i 5v 5v external reference voltage clkx2 v dd 5 5v v dd 3 3.3v x gnd agnd av dd 3.3v recommended analog output circuit 150 w 3.6 m h 164pf output ya, ca, cvbso 150 w 164pf 0.1 m f 0.1 m f 75 w 560 w 560 w Cavcc +avcc 1000pf + + C
? semiconductor MSM7650 34/34 package outlines and dimensions 20.00.2 25.00.2 ^4 $1 ^5 *0 q @4 @5 $0 14.00.2 19.00.2 0.8typ. 1.0typ. 0.32 0.8 C0.07 +0.08 index mark mirror finished surface 0.170.05 0.16 m 0.12 seating plane 2.5typ. 1.3typ. 1.380.15 2.10.2 2.5max. 0.05 to 0.35 0.25 0 to 10?

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